1. Field of the Invention
This invention relates generally to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects that have the minimum pitch and that have the maximum contact area at the electrical interconnections.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required the density of metallization lines to be increased and in addition has required the addition of stacked layers. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but are also conducive to subsequent CMP (chemical mechanical polishing) processing. As the interconnection line widths shrink, the challenges of etching materials using photoresist-as-mask techniques have become increasingly difficult. A major cause of the difficulty is the large aspect ratios involved. The aspect ratio is the ratio of the depth of a feature being etched to the width of the feature (D/W).
One method of forming a trench is a method known as the damascene process, which comprises forming a trench by masking and etching techniques and subsequent filling of the trench with the desired conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advanced semiconductor devices. A dual damascene process is a two step sequential mask/etch process to form a two level structure such as a via connected to a metal line above the via.
Current dual damascene processing technology entails depositing a triple layer sandwich consisting of a thick layer of a dielectric material, an etch stop material having a high etch selectivity to the dielectric layer, and a second thick layer of a dielectric material. The two level structure is formed by masking and etching through the top layer of dielectric material stopping on the layer of etch stop material, etching the etch stop material only, then performing a second masking and etching process with the second masking being an oversize masking. The second etch is to the dielectric material underlying the lower layer of dielectric material.
The increased density has caused a requirement to increase the aspect ratio of the photolithographic processes. However, the current dual damascene process has several problems that prevent the further increase of the aspect ratio. One problem is caused by the formation of a polymer residue during the etch process. A second problem is the limitations of the lithography systems being used to expose the photoresist in the resist-as-mask process.
As discussed above, the dimensions required in current semiconductor processing are extremely small, on the order of 0.5 .mu.m and smaller. As is known in the semiconductor manufacturing art, with wet etching, fine patterning of dimensions of this kind involves forming a resist film in the prescribed pattern on the surface of the layer to be patterned. During the wet etching process, isotropic etching characteristics are exhibited. This causes undercutting in the width direction simultaneously with the etching in the depth direction. This makes it difficult to obtain the desired dimensions making the wet etching process unsuitable. In contrast, with dry etching, the amount of etching in the width direction is very small compared to the amount of etching in the depth direction on the layer to be patterned. Because of this, dry etching is much more suitable for the fine patterning such as that described above.
However, during dry etching, a polymer residue is created and is deposited on surfaces in the etched areas forming a polymer residue layer. The polymer residue layer contains components of the gas used in the etching process, structural components of the patterned layer, including the resist and metal components (for example, iron, chromium and nickel from structural components of the etching equipment). This polymer residue layer cannot be removed by conventional plasma ashing (transliteration) or mixtures of sulfuric acid, hydrogen peroxide and water. These cleaners are used to remove organic contaminants and generally consist of a 3:1 mixture of concentrated sulfuric acid and a 30% mixture of hydrogen peroxide and water.
The presence of the polymer residue layer results in problems such as the following:
1. When a polymer residue layer is formed on the side walls of a contact hole (via), the area of contact between the layers being connected is reduced causing an increase in the contact resistance; PA1 2. When a polymer residue layer is formed, it becomes more difficult to adhere wiring materials to the insulating layer (for example, the interlayer dielectric); PA1 3. When a polymer residue layer is formed, the insulation provided by the interlayer dielectric becomes unreliable; and PA1 4. When the polymer residue layer contains metal components, they may contaminate production facilities, such as electric furnaces or cleaning equipment used in the steps after patterning.
Imaging during the formation of resist structures on a silicon wafer continues to be the driving force in optical and nonoptical microlithography. The test of a successful lithographic process begins with imaging, and once the images are satisfactorily formed, the rest of the process can be developed. While all of the integrated circuit manufacturing process steps are interrelated, imaging is the most critical process step in determining or setting the limits for pattern size and relationship. The historical trend in microelectronics has been one of reducing image size and increasing wafer productivity at the exposure step.
The techniques of wafer imaging in microlithography have undergone considerable change. One method of increasing resolution in wafer imaging lithography is to use shorter wavelength illumination. Optical photolithographic techniques have typically operated on the G, H, and I energy lines of the mercury spectrum, corresponding to the 436, 405 and 365 nanometer wavelengths, respectively. The logical pathway for the further increase of resolution in resist exposure is to move below the wavelengths of the major mercury lines. The benefit of using shorter exposing wavelengths to obtain increased resolution is based on a simple mathematical relationship. In an optical system, resolution is a function of wavelength according to the well-known relationship: EQU .nu..sub.o =2NA/.lambda.,
where .nu..sub.o is cutoff frequency (normalized to unity) in line pairs per mm, NA is the numerical aperture and .lambda. is the wavelength in mm. The numerical aperture is defined as 2NA=1/.function. where .function. is the .function.-number of the optical system and is equal to the focal length/effective diameter. Combining the two equations gives the relationship .nu..sub.o =1/.lambda..function.. From this relationship it can be seen that decreasing the wavelength increases the resolution of the optical system .lambda..
Short wavelength lithography techniques permit finer pattern resolution; however, a number of rules must be obeyed to take advantage of the natural gain in pattern density caused by reduced wavelength. The minimum line width and depth of focus are a function of the numerical aperture and wavelength of the optical imaging tool. For example, at a wavelength of 250 nanometers, the numerical aperture is limited to 0.5, with an accompanying depth of focus of 0.5 .mu.m. The depth of focus should never be greater than the resist thickness or image dimensional variation will occur in the resist. In the resist, the contrast must be high to allow for the formation of high-aspect-ratio images.
FIGS. 1B & 1C illustrate one of the problems when a feature such as a trench has a high aspect ratio. The depth of focus of the lithography system has to be set above the bottom of the trench and results in tapered sides 122. Another cause of the tapered sides 122 is the buildup of a polymer residue layer that deters the etch process and can eventually stop the etch process.
FIGS. 2F-2J illustrate a problem resulting from a process in which a layer of scum 206 is left on the bottom of the trench after the process to etch the resist. FIGS. 2G-2J illustrate the results of an overetching process that is necessary to remove the layer of scum 206 from the bottom of the trench. FIG. 2J shows that the resulting width W.sub.3 of the trench is wider than the desired width W.sub.1, resulting in a decreased density for the semiconductor device.
Therefore, what is needed is a method of manufacturing semiconductor devices that avoids the problems associated with the buildup of a layer of polymer residue and the limitations of the photolithographic systems used in semiconductor processing.